Pick & Place
Chip packaging is undergoing profound change — in placement accuracy, in speed, in process. From lead frame to substrate, wire bond to flip chip, planar to 3D, RDL to TSV. Our work is to keep contributing value inside the Pick & Place step.
Why accuracy keeps tightening
Each packaging generation compresses the placement budget. Conventional epoxy die attach tolerates ±20μm. DAF thermo-compression for memory stacks needs ±10μm. Flip-chip needs ±5μm. HBM and CoWoS push toward ±1μm. Our roadmap tracks that curve directly.
Throughput at the same time
Tighter accuracy usually costs speed. The engineering problem we work on is holding both — which is why the D-MARS 8900 reaches 40K UPH at ±5μm across a 600×600mm panel, roughly three times the throughput of the closest competing platform.